In addition to dramatically simplifying BOM cost and complexity, power savings of 50% or more can be realized by migrating to this new solution. Board space is also minimized since multiple components are replaced with a single IC packaged in a small 4×4 mm 24-QFN package. The Level of jitter performance makes it possible to consolidate data path and control plane clocking into a single device
Frequency Margining for Board-Level Test
Frequency margining is greatly simplified using this approach because the MultiSynth’s fractional divider value can be changed dynamically such that the clock output produces a variable clock source. All frequency transitions are continuous and glitchless. Frequency transitions as small as 1 kHz and as large as 10 MHz are possible using this architecture. The frequency of each output clock can be changed dynamically for any frequency up to 350 MHz. As a result, standalone crystal oscillators traditionally used for board-level test can be eliminated.
Integrated Level Translation
The signal format of each Si5338 output clock is user-programmable to any of the options listed in Figure 8. This functionality eliminates the need to use external level translators in most designs. Further, use in mixed-supply applications is simplified since every Si5338 output clock has an independent supply voltage. Each of the device outputs can be programmed to support any output clock/VDD combination listed below. For example, 1.8 V LVDS, 3.3 V CMOS, and 2.5 V LVPECL can be supported simultaneously. The device core operates from a separate supply voltage operating at 1.8, 2.5 and 3.3 V and is independent of the output clock supply voltage (VDDO0 to VDDO3).
Summary
The Si5338 is the industry’s first clock generator capable of supporting any-rate frequency synthesis on four independent output clocks. By providing this level of frequency flexibility, the Si5338 eliminates the need for fixed-frequency clock generators and discrete crystal oscillators. The device provides outstanding jitter performance of 1 ps RMS, enabling a single device to provide reference timing for physical layer transceivers as well as processors, network processors, FPGAs and memory. Frequency margining is greatly simplified because crystal oscillators at margined frequencies are no longer required. To further reduce BOM cost and complexity, the device supports user-programmable output clock formats, eliminating the need for discrete level translators. The best-in-class performance and integration provided by the Si5338 greatly simplify timing architectures in communication and broadcast video applications.